In order to be able to make integrated circuits (ICs), such as memory devices and logic devices of higher integration density than currently feasible, one needs to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs), and passive structures, such as semiconductor resistors. Scaling achieves compactness and improves the operating performance in devices by shrinking the overall dimensions of the device while maintaining the device electrical properties. Generally, all the dimensions of the device are typically scaled simultaneously in order to optimize its electrical performance.
Polysilicon resistors are widely used in conventional integrated circuit design thanks to their highly accurate resistivity, low temperature coefficiency and low parasitic capacitance. In conventional CMOS technology, polysilicon resistor shares the same polysilicon material, which is also known to be used to form the gate electrode for the transistor. During patterning of the gate electrode structures, resistors can also be formed, the size of which can significantly depend on the basic specific resistance value of the polysilicon material and subsequent type of dopant material and concentration that can be incorporated into the resistors to adjust the resistance values. Conventional resistor properties, such as resistance, temperature coefficients, and the like, change dramatically whenever the gate electrode fabrication process changes affecting the gate height, the gate doping and the gate integration.